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CS98000 DVD On-a-Chip Solution
Features
l
Description
Overall the CS98000 Crystal DVD Processor is targeted as a market specific consumer entertainment processor that empowers new product classes with the inclusion of a DVD player as a fundamental feature. You can use this integrated circuit with all the other Crystal mixed signal data converters, DSPs, and the CS98000's high quality factory firmware to rapidly conceptualize, design, and market cuttingedge Internet age products such as:
* * * * DVD A/V Mini-Systems DVD Players DVD Receivers Car/SUV Entertainment Units
Powerful Dual 32-bit RISCs >160 MIPS l Software based on popular RTOS, C/C++ l MPEG video decoder supports DVD, VCD, VCD 3.0, and SVCD standards l Video input with Picture-in-Picture and zoom l 8-bit multi-region OSD w/vertical flicker filter l Universal subpicture unit for DVD and SVCD l PAL<->NTSC Scaling and Transcoding l Supports SDRAM and FLASH memories l Powerful 32-bit Audio DSP >80 MIPS l Decodes: AC-3, DTS, MPEG Stereo l Plays MP3 CDs l Karaoke echo mix and pitch shift l Optional 3-D Virtual, bass & treble control l Up to 8-channel PCM output l IEC-60958/61937 Out: AC-3, DTS, MPEG l Multi-Mode Serial Audio I/O: I2S & AC-Link l AV Bus or ATAPI interface or DVD/CD/HD l GPIO support for all common sub-circuits
ORDERING INFORMATION CS98000-CM 0 to 70 C
208-pin
RISC-1 I-Cache MMU D-Cache MAC
RISC-2 I-Cache MMU D-Cache MAC
Memory Controller SDRAM Control FLASH Control
32- Bit DSP I-Cache X,Y Data Memory CPU / MAC Audio I/O PCM Out PCM In XMT958 A/V Bus ATAPI-IDE Local Bus
Video Input Scaler Filter MPEG Decoder VLC Parser IDCT RAM MoCo
Clock Manager Dataflow Engine DMA / BitBlit SRAM Buffer External I/Os Remote Input GPIOs
Subpicture Decode Scaler System Controls STC Interrupts Registers SDRAM
Video Processor On-Screen Display Picture-in-Picture Video/Graphics Display
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
NOV `01 DS525PP2 1
CS98000
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 1.1 AC AND DC PARAMETRIC SPECIFCATIONS ................................................................. 5 1.1.1 ABSOLUTE MAXIMUM RATING .......................................................................... 5 1.1.2 RECOMMENDED OPERATING CONDITIONS ................................................... 6 1.1.3 ELECTRICAL CHARACTERISTICS .................................................................... 6 1.2 DC CHARACTERISTICS ................................................................................................... 7 1.2.1 ATAPI Interface ..................................................................................................... 7 1.2.2 SDRAM Interface .................................................................................................. 8 1.2.3 ROM/NVRAM Interface ...................................................................................... 10 1.2.4 Video Output Interface ........................................................................................ 11 1.2.5 Video Input Interface ........................................................................................... 12 1.2.6 Audio Input Interface ........................................................................................... 13 1.2.7 Audio Output Interface ........................................................................................ 14 1.2.8 AC97/CODEC Interface ...................................................................................... 15 1.2.9 Miscellaneous Interface Timing ........................................................................... 16 2. TYPICAL APPLICATION ........................................................................................................ 17 3. FUNCTIONAL DESCRIPTION ............................................................................................... 18 3.1 Block Diagram .................................................................................................................. 18 3.2 CS98000 Device Details .................................................................................................. 18 3.2.1 RISC-32 Processors ........................................................................................... 18 3.2.2 Powerful 24/32-Bit DSP ...................................................................................... 18 3.2.3 System Controls .................................................................................................. 18 3.2.4 Memory Controller ............................................................................................... 19 3.2.5 Data Flow Engine ................................................................................................ 19 3.2.6 MPEG Video Decoder ......................................................................................... 19 3.2.7 System Synchronization ...................................................................................... 19 3.2.8 Audio Interface .................................................................................................... 19 3.2.9 Video Input .......................................................................................................... 19 3.2.10 External Interface .............................................................................................. 19 3.2.11 Video Processor ................................................................................................ 19 3.2.12 Sub-Picture Processor ...................................................................................... 19 3.2.13 System Functions .............................................................................................. 20 3.3 RISC Processor ............................................................................................................... 20 3.4 DSP Processor ................................................................................................................ 20 3.5 Memory Control ............................................................................................................... 20
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic web site or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2C system.
2
CS98000
3.6 Dataflow Control (DMA) ................................................................................................... 20 3.7 System Control Functions ............................................................................................... 21 3.8 DVD/ATAPI Interface ....................................................................................................... 21 3.9 MPEG Video Decoding .................................................................................................... 21 3.10 Audio Processing ........................................................................................................... 21 3.11 Soft Modem ................................................................................................................... 22 3.12 Video ............................................................................................................................. 22 MEMORY MAP ....................................................................................................................... 22 4.1 Processor Memory Map .................................................................................................. 22 4.2 Host Port Memory Map .................................................................................................... 22 4.3 Internal I/O Space Map .................................................................................................... 22 REGISTER DESCRIPTION .................................................................................................... 24 5.1 CS98000 Register Space ................................................................................................ 24 PIN DESCRIPTION ................................................................................................................. 33 6.1 Pin Assignments .............................................................................................................. 34 6.2 Miscellaneous Interface Pins ........................................................................................... 40 6.3 SDRAM Interface ............................................................................................................. 40 6.4 ROM/NVRAM Interface ................................................................................................... 41 6.5 Video Output Interface ..................................................................................................... 41 6.6 Video Input Interface ....................................................................................................... 42 6.7 Audio Output/Input Interface ............................................................................................ 42 6.8 AC97/CODEC Interface ................................................................................................... 43 6.9 Host Master/ATAPI Interface ........................................................................................... 43 6.10 DVD I/O Channel Interface ............................................................................................ 44 6.11 General Purpose Input/Output (GPIO) .......................................................................... 44 6.12 Power and Ground ........................................................................................................ 45 PACKAGE SPECIFICATIONS ............................................................................................... 46
4.
5. 6.
7.
LIST OF FIGURES
Figure 1. ATAPI Transactions - Read and Write............................................................................. 7 Figure 2. SDRAM Refresh Transaction........................................................................................... 8 Figure 3. SDRAM Burst Write Transaction ..................................................................................... 8 Figure 4. SDRAM Burst Read Transaction ..................................................................................... 9 Figure 5. SDRAM Timing ................................................................................................................ 9 Figure 6. ROM/RVRAM Timing..................................................................................................... 10 Figure 7. Video Output Timing ..................................................................................................... 11 Figure 8. Video Input Timing ......................................................................................................... 12 Figure 9. Audio Input Timings ....................................................................................................... 13 Figure 10. Audio Output Timing .................................................................................................... 14 Figure 11. CODEC Timing ............................................................................................................ 15 Figure 12. Miscellaneous Timing .................................................................................................. 16 Figure 13. CS98000 Typical Application ....................................................................................... 17 Figure 14. CS98000 Block Diagram.............................................................................................. 18 Figure 15. CS98000 Pinouts ......................................................................................................... 33 Figure 16. 208-Pin Package Drawing ........................................................................................... 46
LIST OF TABLES
Table 1. ATAPI Interface Symbols / Characterization Data ............................................................ 7 Table 2. SDRAM Interface Symbols and Characterization Data..................................................... 8 Table 3. ROM/NVRAM Interface Symbols and Characterization Data ......................................... 10 Table 4. Video Output Interface Symbols and Characterization Data........................................... 11
3
CS98000
Table 5. Video Input Interface Symbols and Characterization Data.............................................. 12 Table 6. Audio Input Interface Symbols and Characterization Data.............................................. 13 Table 7. Audio Output Interface Symbols and Characterization Data........................................... 14 Table 8. AC97/CODEC Interface Symbols and Characterization Data......................................... 15 Table 9. Miscellaneous Interface Symbols and Characterization Data ......................................... 16 Table 10. Memory Map-RISC0 Processor .................................................................................... 23 Table 11. Host Port Memory Map ................................................................................................. 23 Table 12. Internal IO Space Map .................................................................................................. 23 Table 13. CS98000 Register Map and Blocks .............................................................................. 24 Table 14. CS98000 Registers ....................................................................................................... 24 Table 15. Pin Type Legend ........................................................................................................... 33 Table 16. 208-Pin Package Assignments ..................................................................................... 34 Table 17. Miscellaneous Interface Pins......................................................................................... 40 Table 18. SDRAM Interface .......................................................................................................... 40 Table 19. ROM/NVRAM Interface ................................................................................................. 41 Table 20. Video Output Interface .................................................................................................. 41 Table 21. Video Input Interface ..................................................................................................... 42 Table 22. Audio Input/Output Interface ......................................................................................... 42 Table 23. AC97/CODEC Interface ................................................................................................ 43 Table 24. Host Master/ATAPI Interface......................................................................................... 43 Table 25. DVD I/O Channel Interface............................................................................................ 44 Table 26. General Purpose I/O Interface ...................................................................................... 44 Table 27. Power and Ground ....................................................................................................... 45
4
CS98000
1. CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS (AGND, DGND=0V, all voltages with respect to 0V)
1.1.1 ABSOLUTE MAXIMUM RATING Symbol VDDIO VDDCORE VI II IO TSOL TVSOL TSTOR TAMB PIO PCORE PPLL Description Power Supply Voltage on I/O ring Power Supply Voltage on core logic and PLL Digital Input Applied Voltage (power applied) Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature Vapor Phase Soldering Temperature Storage Temperature (no power applied) Ambient Temperature (power applied) Power consumption on I/O ring (CL = 35 pF) Power consumption on the core logic Power consumption on the PLL logic Min -0,5 -0.5 -0.5 -10 -50 -40 0 Max 4.6 3.6 5.5 10 50 260 220 125 70 57 620 15 Unit Volts Volts Volts mA mA
o
C
oC oC o
C
mA mA mA
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS98000 devices operate at the settings described in the next table.
1.1.2
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VDD VDD TAMB Min 3.0 2.25 0 Typ 3.3 2.5 25 Max 3.6 2.75 70 Units Volts Volts
oC
Supply Voltage, IO Supply Voltage, core and PLL Ambient Temperature(power applied)
5
CS98000
1.1.3
ELECTRICAL CHARACTERISTICS
Parameter Symbol IDD IDD VIH VIL IIN RI VOH VOL IOZ CIN COUT CBID @ buffer rating @ buffer rating VOUT = VSS or VDD VIN = VDD or VSS Conditions Normal Operating Normal Operating Min 2.0 -1 2.4 -10 3 3 Typ 45 550 75 3 Max 5.0 0.8 +1 0.4 +10 6 6 Units mA mA Volts Volts A K Volts Volts A pF pF pF
Supply Current, IO Supply Current, core and PLL Input Voltage, High Input Voltage, Low Input Current Input Pull up/down resistor Output Voltage, High Output Voltage, Low Three-state Leakage Input Capacitance Output Capacitance Bidirect Capacitance
6
CS98000
1.2 DC CHARACTERISTICS (TA= 25C; VDD_PLL=VDD_CORE=2.5V10%, VDD_IO=3.3V10%)
1.2.1 ATAPI Interface
CS98000 can interface with a ATAPI-type slave loader gluelessly. Figure 1 illustrates a read ATAPI transaction and a write ATAPI transaction. PIO mode 4 is implemented to enable a sufficient data transfer rate between ATAPI device and CS98000.
Note: ATAPI interface is a standard administered by the T13 committee that is responsible for all interface standards relating to the AT Attachment (ATA) storage interface. T13 is a technical committee for the National Committee on Information Technology Standards (NCITS).See http://www.t13.org/. Symbol
t
Description Cycle Time
1
Min 70 20 70 25 20 10 20 5 0 35
Typ
Max
Unit ns ns ns ns ns ns ns ns ns ns
acyc aavr
t
Address Valid to HMRD-/HMWR- Setup H_RD-/H_WR- Pulse Width H_RD-/H_WR- Recovery Time H_WR- Data Setup H_WR- Data Hold H_RD- Data Setup H_RD- Data hold Read Data Valid to H_RDY Active H_RDY Setup Time H_RDY Pulse Width H_RDY Assertion to Release
tarww tarec tawsu t t
awh
ardsu
tardr tarsu
tarddh
t
aipw
tarls
1250 5
ns ns
Table 1. ATAPI Interface Symbols / Characterization Data 1.Values are guaranteed by design only.
tacyc H_A[4:0] taavr H_RD-/H_WRtarww tarec
H_D[15:0](WRITE) tawsu H_D[15:0](READ) tarsu H_RDY(deasserted before tarsu) tarar H_RDY(asserted before tarsu) taipw
Dout
tawh
Din
tardsu tarddh
tardr
tarls
Figure 1. ATAPI Transactions - Read and Write
7
CS98000
1.2.2 SDRAM Interface
CS98000 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure 2 shows the refresh cycle performed by CS98000. Figure 3 shows a burst write (length = 8) transaction. Figure 4 on page 9 shows a burst read (length = 8) transaction, while Figure 5 on page 9 shows detailed SDRAM interface timing. In both Figure 3 and Figure 4, CAS latency is programmed to 3.
Symbol tmsur tmhr tmco tcch tccl tmper tmhw tmdow tmsuw Description M_D[31:0] setup to M_CKO M_D[31:0] hold time after M_CKO M_CKO active edge to Output transition M_CKO high time M_CKO low time M_CKO Period1 M_D[31:0] valid time after M_CKO M_D[31:0] delay from M_CKO rising edge M_D[31:0] valid time prior to M_CKO 4 4.5 4.5 10 5 5 12.5 Min 3 1 7 Typ Max Unit ns ns ns ns ns ns ns ns ns
Table 2. SDRAM Interface Symbols and Characterization Data 1.Values are guaranteed by design only.
M_CKE M_A_[11:0] M_BS_N M_RAS_N M_CAS_N M_WE_N MD[31:0] M_DQM_[3:0] M_AP
Figure 2. SDRAM Refresh Transaction
M_CKO M_A_[11:0] M_BS_N M_RAS_N M_CAS_N M_WE_N M_D_[31:0] M_DQM_[3:0] M_AP D0 D1 D2 D3 D4 D5 D6 D7 R0 C0 C1 C2 C3 C4 C5 C6 C7
Figure 3. SDRAM Burst Write Transaction
8
CS98000
M_CKO M_A_[11:0] M_BS_N M_RAS_N M_CAS_N M_WE_N M_D_[31:0] M_DQM_[3:0] M_AP D0 D1 D2 D3 D4 D5 D6 D7 R0 C0 C1 C2 C3 C4 C5 C6 C7
Figure 4. SDRAM Burst Read Transaction
tmco M_CKO M_RAS_N,M_CAS_N M_WE_N,M_AP,M_DQM[3:0], M_CKE,M_A[11:0] M_D[31:0](WRITE)
tmper
tcch
tccl
tmdow
tmhw
M_D[31:0](READ) tmsur tmhr tmsuw
Figure 5. SDRAM Timing
9
CS98000
1.2.3 ROM/NVRAM Interface Symbol
t t t t t t
Description M_CKO period1 M_CKO to WE or OE out M_CKO to write data out Data setup to M_CKO Data hold from WE inactive Data hold from OE inactive
Min 10
Typ 12.5
Max 15 10
Unit ns ns ns ns ns ns
mper
nco nwdo nsur nhw nhr
5 5 1
Table 3. ROM/NVRAM Interface Symbols and Characterization Data 1.Values are guaranteed by design only.
Figure 6. ROM/RVRAM Timing
10
CS98000
1.2.4 Video Output Interface Symbol tsuvo tcovo1 tcovo2 tvoch tvocl Description Vsync/Hsync input setup to CLK27_O VDAT[7:0] delay from CLK27_O transition Vsync/Hsync delay from CLK27_O transition CLK27_O High Time1 CLK27_O Low Time1 14.8 14.8 18.5 18.5 Min 5 10 10 22.2 22.2 Typ Max Unit ns ns ns ns ns
Table 4. Video Output Interface Symbols and Characterization Data 1.Values are guaranteed by design only
CLK27_O (Output) Tvocl Tvoch Tcovo1 VDAT[7:0] (Output) Tcovo2
VSYNC/HSYNC (Output)
VSYNC/HSYNC (Input)
Tsuvo
Figure 7. Video Output Timing
11
CS98000
1.2.5 Symbol tsuvi thvi tvich tvicl Video Input Interface Description VIN_D[7:0] set up to VIN_CLK VIN_D[7:0] hold time after VIN_CLK rising edge VIN_CLK High Time1 VIN_CLK Low Time1 1.Active clock edge is programmable. Timing is referenced from active edge Min 5 2 14.8 14.8 18.5 18.5 22.2 22.2 Typ Max Unit ns ns ns ns
Table 5. Video Input Interface Symbols and Characterization Data
.
tvicl VIN_CLK tsuvi VIN_D[7-0] thvi
tvich
VIN_HSNC,VIN_VSNC, VIN_FLD
Figure 8. Video Input Timing
12
CS98000
1.2.6 Symbol taicl taich taiper tstlr tlrts tsdsus tsdhs AIN_BCK Low Time1, AIN_BCK period1, 2 Time form AIN_LRCK transition to AUD_BCK active edge Time form AIN_LRCK transition to AIN_BCK active edge AIN_DATA setup to AIN_BCK transition AIN_DATA hold time after AIN_BCK transition
2
Audio Input Interface Description AIN_BCK High Time1, 2 Min 14 14 162.7 5 2 5 2 Typ Max Units ns ns ns ns ns ns ns
Table 6. Audio Input Interface Symbols and Characterization Data 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge
t aiper t aich AIN_BCK (Input) t lrts AIN_LRCK (Input) t sdsus AIN_DATA (Input)
Figure 9. Audio Input Timings
t aicl
t stlr
t sdhs
13
CS98000
1.2.7 Audio Output Interface Min 4.5 4.5 13
1, 2
Symbol Description taxch AUD_XCLK High Time (AUD_XCLK is Input/Output)1, 2 taxcl AUD_XCLK Low Time (AUD_XCLK is Input/Output)1, 2 taxper taoch taocl taoper tsdm tsdm tlrds tadsm AUD_XCLK period (Input/Output)
1, 2
Max -
Units ns ns ns ns ns ns
AUD_BCK High Time for Master mode AUD_BCK Low Time for Master mode
14 14 162.7 -
1, 2
AUD_BCK period (Output)1, 2 AUD_BCK delay from AUD_XCLK transition AUD_BCK delay from AUD_XCLK transition AUD_LRCK delay from AUD_BCK transition AUD_D[3:0] delay from AUD_BCK transition
2 2 2 2
ns ns ns ns
Table 7. Audio Output Interface Symbols and Characterization Data 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge
t AUD_XCLK(Input/Output) t AUD_BCK(Output) t
sdm axch
axper
t
axcl
t aoperl t aoch AUD_BCK(Output) t aocl
t AUD_LRCK(Output) t adsm AUD_DO[3:0] (Output)
lrds
Figure 10. Audio Output Timing
14
CS98000
1.2.8 Symbol tsuc thc tcoc tcch tccl tccper AC97/CODEC Interface Description Data set up to CDC_CK Data hold time after CDC_CK Time from active edge of CDC_CK to Data transition CDC_CK High Time1, CDC_CK Low Time1, 2 CDC_CK period1, 2
2
Min 5 1
Typ
Max
Units ns ns
10 14 14 162.7
ns ns ns ns
Table 8. AC97/CODEC Interface Symbols and Characterization Data 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge
t ccper t ccl CDC_CK (Intput) CDC_DO, CDC_SY, CDC_Rst (Output) t coc t cch
t suc CDC_DI, CDC_SY (Input)
t hc
Figure 11. CODEC Timing
15
CS98000
1.2.9 Miscellaneous Interface Timing Symbol txccl txcch txccper trstl tgpl tgpl Description XTLCLOCK Rise Time XTLCLOCK Fall Time XTLCLOCK period1 RESET_N Pulse Width GPIO PW Low GPIO PW High XTLCLOCK/RESET_N Rising Time XTLCLOCK/RESET_N Falling Time Table 9. Miscellaneous Interface Symbols and Characterization Data 1.XTLCLOCK must meet the requirement of external the video encoder for correct chroma. Min 4.5 4.5 14.8 1000 50 50 5 5 18.5 22.2 Typ Max Units ns ns ns ns ns ns ns ns
t txccl XTLCLOCK
xccper
t xcch
trstl RESET-N tgph tgpl
GPIO
Figure 12. Miscellaneous Timing
16
CS98000
2. TYPICAL APPLICATION
The Figure 13 shows a typical example of a complete Internet-DVD solution using the CS98000.
Remote Keyboard/ Control
Front Panel
DAA
IR
Phone Line Parallel Port Audio-L(3) Audio-R(3)
Driver
CODEC
Audio-L Audio-R Video
Audio ADC Video Decoder
CS98000
(3)Audio DACs
S/PDIF
Video Encoder FLASH .5-2MB FLASH 2MB SDRAM 4-8MB SDRAM 8MB Power Reg.
DVD Loader (I/O Chan) or ATAPI Loader + Hard Drive*
S-Video Composite Video Switch Power
* Hard drive useable with ATAPI loader
Figure 13. CS98000 Typical Application
17
CS98000
3. FUNCTIONAL DESCRIPTION
3.1 Block Diagram The CS98000 block diagram is shown in Figure 14. 3.2
3.2.1 * * * * * * * 3.2.2 * Powerful 24/32-Bit DSP Powerful 24/32 bit DSP processor, programmable through CS98000 API, See CS98000 Software API, (DS525UM1) 24-bit fixed point logic, with 54-bit accumulator Single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic. 8-Kbyte instruction cache, 8-Kbyte program visible local memory Single cycle instructions, runs at 81 Mhz System Controls Includes several hardware lockable semaphore registers General-purpose register for inter-processor communication 32-bit timers for I/O and other uses, with programmable interval rates
CS98000 Device Details
RISC-32 Processors Two Powerful 32-bit RISC processors (RISC0 and RISC1) Virtual memory support Optimizing C compiler Big or little endian data formats support MAC multiply/accumulate in 2 cycles with C support 4 Kbyte instruction cache, 2 Kbyte data cache Single cycle instructions, runs at 81 Mhz
* *
* * * *
3.2.3
Figure 14. CS98000 Block Diagram
18
CS98000
* * Both hardware and software interrupts on data or debug Built in PLLs generate all required clocks from 27 Mhz input clock Memory Controller * Supports SDRAM, and SGRAM, from 2 Mbytes to 32 Mbytes Supports multiple banks of FLASH and ROM up to 16 Mbytes 32-bit data bus for DRAM, 8 or 16-bit data bus for ROM Data Flow Engine * * 2432 bytes of internal memory DMA to/from main RAM into local SRAM Supports endian conversion and byte, short, long data formats on DMA Supports block transfers for graphics bit blits MPEG Video Decoder * Supports VCD, VCD 3.0, SVCD, DVD video standards Supports trick features, including smooth 2x play and reverse play Special anti-tearing logic controls picture decode and presentation Advanced error concealment hardware System Synchronization * System time clock (STC) for audio/video synchronization Flexible interrupt structure for controlling decode and presentation times Hardware scheduling of subpicture and highlight events Audio Interface Supports PCM, I2S and IEC-958 outputs at up to 96 KHz output rate 8 output channels, 2 input channels Video Input NTSC/PAL video decoder input interface Built in variable down scaling, handles CCIR 601 to QCIF input formats Video input image can be displayed in small window, or as main picture External Interface Serial I2C(R) master and slave port * * * 29 independent fully programmable bi-directional I/O pins 8 edge or level detection interrupt pins Hardware assisted support for infrared remote devices, such as remote control, infrared keyboard, mouse, printer, and more Programmable parallel host master and slave interface supports many formats including ATAPI, ISA, and more IO channel interface supports standard DVD loader protocols Serial interface supports AC-97 and other standard MODEM CODEC protocols Video Processor Supports 24-bit 4:2:0 and 4:2:2 video modes and 16-bit true color graphics modes. On screen display module supports 2-bit, 4-bit, or 8bit pixel modes, while supporting 3 separate regions and 16 transparency overlay levels Picture-in-picture module includes horizontal and vertical downscaling with programmable output sizes, positions, and borders Overlay mixer with RGB to YUV conversion and output formatting Supports 4:2:0, 4:2:2, YUV655, RGB565 and RGB555 frame buffer inputs Outputs 4:2:2 video in CCIR-601 or CCIR-656 format High quality scaling using a vertical and a horizontal 16 taps polyphase programmable filter and supports any size image up to 768x576 Programmable sharpening and de-blocking filters 5 taps programmable adaptative anti-flicker filtering for graphics source Master or Slave video sync configuration Multiple video plains overlay (main video / video input / picture_in_picture / picture/on_screen / display/cursor) Gamma correction Sub-Picture Processor Run-length decode DVD sub-pictures and SVCD OGT formats Hardware vertical scaling supports NTSC-PAL format conversion 16-level alpha blending Provides hardware cursor mode for non-DVD applications
3.2.4 * * *
* *
3.2.5 * * * * * * * * * * *
3.2.11
3.2.6
* * *
3.2.7
* * * *
3.2.8 * * * * *
* * * * *
3.2.9
3.2.12
3.2.10 *
19
CS98000
3.2.13 * * * * * System Functions 208-pin PQFP packages All I/O pins are 3 V with 5 V tolerance Advanced 0.25 micron CMOS technology Internal processors run at 81 MHz Supports Low Power modes and clock shutoff
tions. The interface to main memory is designed for handling flexible block sizes and skip counts. 3.5 Memory Control The DRAM Interface performs the SDRAM control and arbitration functions for all the other modules in the CS98000. The DRAM interface services and arbitrates a number of clients and stores their code and/or data within the local memory. This arbitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. The DRAM Interface supports up to 32 Mbytes. For a typical DVD player application, CS98000 requires 8 Mbytes memory space. Sharing the same interface, CS98000 also supports FLASH ROM, OTP, or mask ROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside SDRAM for execution. The FLASH ROM interface is provided so that the code can be upgraded in the field once the communications channel is established (via modem port, CD-R, or serial port). Utility software will be provided to debug and upgrade code for the system manufacturer. 3.6 Dataflow Control (DMA) The DMA controller moves data between the external memory and internal memory. The external memory address can be specified using a register, or in FIFO mode, using start and end address registers. Separate start/end address registers are used for DMA read and write operations. The DMA interface also has a block transfer function, which allows for the transfer of one block of data from one external memory location to another external memory location. In effect, this feature combines a DMA read and write into one operation. In addition, the DMA write operation allows for byte, short, word, and other types of masking. 3.7 System Control Functions The system control functions are used to coordinate the activities of the multiple processors, and to pro-
3.3 RISC Processor The CS98000 includes two powerful, proprietary 32-bit RISC processors, RISC0 and RISC1, with optimizing C compiler support and source level debugger. The RISC processors fully support many Real Time Operation Systems (RTOS). The DVD application user interface resides on RISC1 and is customer programmable. The real time control of low level DVD functions is performed by RISC0. RISC1 gains access to system resources controlled by RISC0 via calls through an Applications Programming Interface, (see the CS98000 Software API). All RISC0 firmware, API and sample application code are supplied with the CS98000. The RISC processors also have a MAC engine, which performs multiply/accumulate in 2 cycles in a pipelined fashion with C support, effectively achieving single cycle throughout. The RISC0 processor coordinates on-chip multi-threaded tasks, as well as system activities such as remote control and front panel control. The DVD application end-user interface resides on RISC1, and any modifications to that interface occur through the CS98000 API. 3.4 DSP Processor The CS98000 contains a proprietary digital signal processor (DSP), which is optimized for audio applications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. There are 32 generalpurpose registers, and eight independent address generation registers, featuring: linear and circular buffer operations, and dual operand read from memory. The multiply-accumulator has single-cycle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking opera-
20
CS98000
vide the supporting system operations. Four 32-bit communication registers are available for interprocessor communication, and eight semaphore registers are used for resource locking. Timers are available for general-purpose functions, as well as more specialized functions such as watchdog timers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. An I2C master allows for control of other I2C devices, such as a video encoder. An I2C slave port shares the same pins, and can be used for debug functions. Interrupts can be generated on specific or generic events. Infrared inputs can be filtered to make them free of glitches or stored unfiltered into memory. Control of all the internal clocks is also possible. Internal PLLs are used to generate the internal system and memory clocks and audio clocks of any widely used frequency. 3.8 DVD/ATAPI Interface The CS98000 has a programmable interface port which can be configured to connect to industry standard CD/DVD loaders without external glue logic. The CD/DVD interface fully supports many popular CD/DVD loaders. The interface consists of DVD control and data ports and an optional CD control/data port. The CS98000 hardware manages the DVD interface and moving data to an arbitrary size input FIFO in DRAM. The same interface pins can be optionally configured as a generic 16-bit host master port. In this mode, the CS98000 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to connect directly to any ATAPI DVD loader (using two chip selects). Simultaneously, the other two chip selects can be configured to connect to other devices, such as a super I/O chip or hard disk. A third option is to configure the interface for micro-less DVD loader operation, which may also be configured to connect without external glue logic. 3.9 MPEG Video Decoding Compressed MPEG data is read from the DVD disk into an input FIFO in DRAM. The data flow (DMA) controller moves Video packets from the input FIFO into the MPEG decoder's input FIFO (also in DRAM). The DMA controller can also perform advanced functions such as start code search, relieving the RISC processors. The System Synchronization function is used to control the timing of MPEG picture decoding. The MPEG Video decoder processes I, B, and P frames, and writes to video frame buffers in DRAM for output to the display. Special anti-tearing logic ensures that currently displayed frame buffers are not overwritten. 3.10 Audio Processing Compressed Audio data is read from the DVD disk into an input FIFO in DRAM. The data is decompressed, then written to a PCM output FIFO, also in DRAM. Presentation time stamps (PTS) are extracted from the stream to update the STC, in order to maintain audio/video synchronization. The DMA and decompression stages of audio processing can be done with a combination of the DMA unit, DSP, and RISC processors. The DSP is optimized for audio processing, so most common formats can be handled by the DSP alone, including AC-3, DTS, MPEG2 audio, and MP3. The DSP has enough reserve bandwidth to handle the Karaoke echo-mix and pitch shift, and AC-3 downmix functions. The audio output data is written into a DRAM FIFO in 16-, 18-, 20- or 24-bit PCM format. A flexible audio output stage can simultaneously output 8 channels of PCM data to audio DACs, or 6 channels of audio data plus an IEC-958 encoded output, at up to 96 KHz. The audio interface also includes a flexible PCM input interface, which can input a
21
CS98000
wide range of protocols from an audio ADC or an IEC-958 receiver. 3.11 Soft Modem The soft modem processing is handled by one of the RISC processors, which is typically dedicated for that function. Data rates up to 56 Kbits (V.90 protocol) are supported. The CS98000 interfaces to a simple external CODEC/DAA circuit using a flexible serial interface. The serial interface is a fully programmable, bi-directional interface and can be used either as a PCM interface or as an AC97 interface. In PCM mode, the sample size could be adjusted to 20, 18 or 16 bits to match common DAC and ADC formats, or any other specific size. In AC97 mode, any slot can be used to interface either a modem CODEC or an audio CODEC. 3.12 Video The Digital Video Interface provides flexible and powerful means of outputting digital video data to external devices in CCIR601/3 and CCIR656 formats. The interface directly supports NTSC/PAL video encoding, in both master and slave synchronization configurations. The internal frame buffer format could be 4:2:0, 4:2:2, YUV655, RGB565 and RGB555. Cirrus Logic provides some easy-touse utilities in order to get the best advantage of the powerful video filtering capabilities of the CS98000. The CS98000 also features an NTSC/PAL video decoder input interface. The interface accepts CCIR601, CIF, and QCIF formats, out of many TV decoders on the market. The video processor also allows overlay of multiple video planes (main video / video input / picture_in_picture / on_screen display / cursor). CS98000 has been proven to work with many TV encoders on the market with brands such as: Crystal, Brooktree, ADI, and AVS. The Video Input Scaler (VIS) module inputs 8-bit digital video data from a camera or PAL/NTSC decoder, optionally down-scales to SIF or QSIF, and stores the data in one to three DRAM frame buffers. The scaled image, with a border, can be overlaid anywhere on the screen into a 1/2 or 1/4-screen sized window by the Picture in Picture (PIP) module. An alternate method of using the Video Input function is to input a full sized picture and present it on the screen full size (bypass mode). In this mode, the PIP module can place full motion DVD images in the small window. An internal glitch-free mux can switch the video processor clock source from the internal clock to the Video Input clock, allowing the PIP mode to switch back and forth on the fly, with no dropout.
4. MEMORY MAP
4.1 Processor Memory Map The CS98000 externally supports up to 32 Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table 10, Table 11 and Table 12 on the next page list the memory map as viewed by the RISC processors, and identifies whether each segment is mapped or cacheable. For detailed information on programming CS98000 memory, see CS98000 Memory Interface User's Manual (DS525UMD1). 4.2 Host Port Memory Map Table 11 on page 23 lists the memory map as viewed by host slave port. 4.3 Internal I/O Space Map Table 10, Table 11, and Table 12 show how the Internal I/O space is mapped between general registers, internal SRAM ports, and the RISC processors' debug port.
Processor Byte Address
Description
Cacheable
Table 10. Memory Map-RISC0 Processor 22
CS98000
0000_0000 - 07FF_FFFF 8000_0000 - 81FF_FFFF 9400_0000 - 9CFF_FFFF 9C00_0000 - 9CFF_FFFF 9D00_0000 - 9DFF_FFFF A000_0000 - A1FF_FFFF B000_0000 - B003_FFFF B400_0000 - BCFF_FFFF BC00_0000 - BCFF_FFFF BD00_0000 - BDFF_FFFF C000_0000 - FFFF_FFFF DRAM (mapped) DRAM (32 Mbytes) 16-bit NVRAM write (16 Mbytes) 16-bit NVRAM/ROM (16 Mbytes) 8-bit NVRAM/ROM (16 Mbytes) DRAM (32 Mbytes) Internal I/O (256 Kbytes) 16-bit NVRAM write (16 Mbytes) 16-bit NVRAM/ROM (16 Mbytes) 8-bit NVRAM/ROM (16 Mbytes) DRAM (mapped) Table 10. Memory Map-RISC0 Processor Host Byte Address 0000 0000 - 003F FFFF 1000 0000 - 13FF FFFF 1400 0000 - 17FF FFFF Internal I/O Space DRAM space (16 Mbytes) NVRAM space (16 Mbytes) Table 11. Host Port Memory Map Description Y Y N Y Y N N N N N Y
Byte Address Offset 0_0000 - 0_2FFF 0_3000 - 1_FFFF 2_0000 - 2_FFFF 3_0000 - 3_FFFF General registers
Description General Internal SRAM RISC_0 Internal SRAM/Registers RISC_1 Internal SRAM/Registers Table 12. Internal I/O Space Map
23
CS98000
5. REGISTER DESCRIPTION
5.1 CS98000 Register Space Table 13 lists the register groups, and how they are split among the main CS98000 functional blocks. Table 14 lists all the registers for the CS98000 and their addresses, and indicates whether the registers are read/write (R/W), read only (RO), or write only (WO).
CS98000 Register 000xx, 010xx 001xx 002xx 003xx 004xx 005xx 006xx 007xx 008xx 009xx 00Axx 00Bxx 00Cxx 00Dxx 00Exx 02xxxx General Host DRC DMA
Block
DVD Interface Serial Interface DSP Synchronization Control MPEG Video Decoder Video Input Scaler Picture-in-picture Video Processor Subpicture Display On-screen Display PCM In/Out RISC_0
03xxxx RISC_1 Table 13. CS98000 Register Map and Blocks
Address 000 010 014 018 10C 020 024 028 02C 030 034
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W General General General General General General General General General General General
Function Command
Register Name InterProc_Comm_Register_0 InterProc_Comm_Register_1 InterProc_Comm_Register_2 InterProc_Comm_Register_3 Semaphore_Register_0 Semaphore_Register_1 Semaphore_Register_2 Semaphore_Register_3 Semaphore_Register_4 Semaphore_Register_5
Table 14. CS98000 Registers
24
CS98000
038 03C 040 044 048 04C 050 054 058 05C 060 064 1040 1044 1048 104C 1050 1054 1058 105C 1060 1064 1068 106C 1070 1074 1078 107C 068 06C 070 074 078 07C 080 084 088 08C 090 094 R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W WO R/W RO R/W WO General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General Semaphore_Register_6 Semiphore_Register_7 GenIO_Read_Data GenIO_Write_Data GenIO_Three_State_Enable GenIO_Positive_Edge GenIO_Negative_Edge GenIO_Interrupt_Status GenIO_Positive_Edge_Mask GenIO_Negative_Edge_Mask GenIO_Level_Mask GenIO_Mode Register GenIOMIS_Read_Data GenIOMIS_Write_Data GenIOMIS_Three_State_Enable GenIOMIS_Positive_Edge GenIOMIS_Negative_Edge GenIOMIS_Interrupt_Status GenIOMIS_Positive_Edge_Mask GenIOMIS_Negative_Edge_Mask GenIOMIS_Level_Mask GenIOMIS_Mode Register GenIODVD_Read_Data GenIODVD_Write_Data GenIODVD_Three_State_Enable GenIOHST_Read_Data GenIOHST_Write_Data GenIOHST_Three_State_Enable I2C_Mstr_Read_Comand I2C_Mstr_Write_1Byte I2C_Mstr_Write_2Bytes I2C_Mstr_Control I2C_Mstr_Status I2C_Mstr_Read_Data RSK0_Interrupt_Mask RSK0_Interrupt_Set RSK0_Interrupt_Status RSK0_Interrupt_Cause DSP_Interrupt_Mask DSP_Interrupt_Set
Table 14. CS98000 Registers (Continued)
25
CS98000
098 09C 0A0 0A4 0A8 0AC 1080 1084 1088 108C 10A0 10A4 10A8 10AC 0B0 0B4 0B8 0BC 0C0 0C4 0C8 0CC 0D0 0D4 0D8 0E0 0E4 0E8 0EC 0F0 10F0 0F4 10F4 0F8 0FC 100 104 108 10C 110 114 R/W RO R/W WO R/W RO R/W WO R/W RO R/W WO R/W RO R/W WO R/W RO R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General General Host Host Host Host Host Host DSP_Interrupt_Status DSP_Interrupt_Cause RSK0_Interrupt_Mask2 RSK0_Interrupt_Set2 RSK0_Interrupt2_Status RSK0_Interrupt_Cause2 RSK1_Interrupt_Mask RSK1_Interrupt_Set RSK1_Interrupt_Status RSK1_Interrupt_Cause RSK1_Interrupt_Mask2 RSK1_Interrupt_Set2 RSK1_Interrupt2_Status RSK1_Interrupt_Cause2 DSP_Interrupt_Mask2 DSP_Interrupt_Set2 DSP_Interrupt2_Status DSP_Interrupt_Cause2 Timer_0 Timer_1 Timer_2 Timer_3 Timer_Control Performance_Monitor_Count Timer_M_Over_N IR_Control IR_Dram_Start_Address IR_Dram_End_Address IR_Dram_Write_Address PLL_Control_Register1 Low_Power_Clock_Control PLL_Control_Register2 PLL_Control_Register3 PLL_Turn_Off PLL_Clock_Divider Device_1_Control Device_2_Control Device_3_Control Device_4_Control Write_Data_Port Read_Data_Port
Table 14. CS98000 Registers (Continued)
26
CS98000
120 124 128 12C 13C 200 204 208 20C 210 214 218 21C 220 224 300 304 308 30C 310 314 318 31C 328 32C 330 334 338 33C 400 404 408 40C 410 414 418 41C 438 440 444 448 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO WO R/W RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W RO R/W RO R/W Host Host Host Host Host DRAM controller DRAM controller DRAM controller DRAM controller DRAM controller DRAM controller DRAM controller DRAM controller DRAM controller DRAM controller DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD SER/DCI SER/DCI SER/DCI Host_Start_Address DRAM Start Address Stream_Transfer_Size DRAM_Burst_Threshold Host_Master_Control DRAM_Controller_Priority0 DRAM_Controller_Priority1 DRAM_Controller_Priority2 DRAM_Controller_Priority3 DRAM_Controller_Priority4 DRAM_Controller_Setup DRAM_Command DRAM_Controller_Mb_Width DRAM_Controller_Debug_Control DRAM_Debug_Status DMA_Enable DMA_Control DMA_Status Xfer_Byte_Cnt Dram_Byte_Start_Addr Sram_Byte_Start_Addr Fifo_Start_Rd_Addr Fifo_Start_Wr_Addr Search_Control Search_Status Fifo_End_Rd_Addr Fifo_End_Wr_Addr Lines_and_Skip Byte_Mask_Pattern DVD1 _Control DVD1 _Fifo_Base_Address DVD1_Fifo_Size DVD1_Sector DVD1_Start_of_Sector DVD1_Current_Dram_Address CD_Control CD_Error_Status DVD1_Status DCI_Control_Reg DCI_Status DCI_Dram_Rd_Start_Addr
Table 14. CS98000 Registers (Continued)
27
CS98000
44C 450 454 458 45C 540 544 548 54C 550 554 558 55C 560 564 568 56C 570 574 578 57C 580 584 588 600 604 6XX 700 704 708 70C 710 714 718 71C 720 724 728 72C 730 734 R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W RO R/W R/W R/W R/W R/W R/W R/W WO WO RO R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI SER/DCI DSP DSP DSP Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control DCI_Dram_Wr_Start_Addr DCI_Nbytes_Sent DCI_Mbytes_Switch DCI_Diagnostic DCI_Active Serial_Frame_Sync_Control Serial_Output_Input_Control AC97_Codec_Control AC97_Codec_Command Serial_Output_Fifo_Start_Address Serial_Output_Fifo_End_Address Serial_Input_Fifo_Start_Address Serial_Input_Fifo_End_Address Serial_Output_Fifo_Read_Address Serial_Input_Fifo_Write_Address Serial_Clock_Synthesis_Parameters Codec_Register_Status Slot5_Register_Data Slot10_Register_Data Slot11_Register_Data Slot12_Register_Data Out_fifo_int In_fifo_int Rate_Control DSP_Boot_Code_Start_Address DSP_Run_Enable DSP_Program_CntRun_Status Audio_Sync_Control Video_Sync_Control Video_Sync_Status Wait_Line Frame_Period STC_Interval System_Time_Clock Top_Bits Video_PTS_FIFO_Start_Address Video_PTS_FIFO_End_Address Video_PTS_FIFO_Write_Address Video_PTS_FIFO_Read_Address Subpicture_PTS_FIFO_Start_Address Subpicture_PTS_FIFO_End_Address
Table 14. CS98000 Registers (Continued)
28
CS98000
738 73C 740 744 748 74C 750 754 758 75C 760 764 768 76C 770 774 778 77C 800 804 808 80C 810 814 818 81C 820 824 828 82C 830 834 83C 840 844 848 84C 854 858 900 904 R/W RO R/W R/W R/W RW R/W R/W RO RO RO R/W R/W R/W RO R/W WO WO R/W R/W R/W R/W RO RO WO RO R/W RO RO R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control Synchronization Control MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder MPEG Video Decoder Video Input Scaler Video Input Scaler Subpicture_PTS_FIFO_Write_Address Subpicture_PTS_FIFO_Read_Address Highlight_Start_PTS Highlight_End_PTS Button_End_PTS Highlight_Control_Information_Address Video_PTS Audio_PTS Subpicture_PTS Audio_Time Video_Sync_Debug SP_DRC_VPTS_Debug Frame_Count_Interrupt Video_DTS Sync_Interrupt_Status Sync_Interrupt_Control Sync_Interrupt_Set Sync_Interrupt_Clear MPEG_Video_Control MPEG_Video_Setup MPEG_Video_FIFO_Start_Address MPEG_Video_FIFO_End_Address MPEG_Video_FIFO_Current_Address MPEG_Video_Horiz_Pan_Vector MPEG_Video_FIFO_Add_Bytes MPEG_Video_FIFO_Curr_Bytes MPEG_Video_FIFO_Interrupt_Bytes MPEG_Video_FIFO_Total_Bytes MPEG_Video_Status Macroblock Width_Height MPEG_Video_Debug MPEG_U_Offset MPEG_I_Base_Register MPEG_P_Base_Register MPEG_Dest_Control MPEG_Software_Flags MPEG_V_Offset MPEG_AntiTearWindow MPEG_Error_Pos VIS_Control VIS_StartX
Table 14. CS98000 Registers (Continued)
29
CS98000
908 90C 910 914 918 91C 920 A00 A04 A08 A0C A10 A14 A18 A1C A20 A24 A28 A2C A30 A34 B00 B04 B08 B0C B10 B14 B18 B1C B20 B24 B28 B2C B30 B34 B38 B3C B40 B44 B48 B4C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO WO WO Video Input Scaler Video Input Scaler Video Input Scaler Video Input Scaler Video Input Scaler Video Input Scaler Video Input Scaler Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Picture-in-Picture Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor VIS_EndX VIS_StartY VIS_EndY VIS_Frame_Base VIS_U_Offset VIS_V_Offset VIS_Frame_Size PIP_Control PIP_VidBrdStartX PIP_VidBrdEndX PIP_VidBrdStartY PIP_VidBrdEndY PIP_BorderClr PIP_Vscale PIP_Line_Offnum_Bot PIP_FrBaseY PIP_FrBaseU PIP_FrBaseV PIP_Line_Width PIP_ Line_Offnum_Top PIP_Frame_Size Video_Processor_Control Video_DRAM_Line_Length Display_ActiveX Display_ActiveY Blank_Color Internal_Hsync_Count Internal_Vsync_Count Horizontal_Y_Offset Horizontal_UV_Offset Vertical_Offset Video_Line_Size Frame_Buffer_Base Video_Line_Mode_Buffer Horizontal_Vertical_Filter Source_X_Offset Horizontal_Video_Scaling Frame_V_Buffer_Compressed_Offset Mb_Width Anti-Flicker Anti-Flicker
Table 14. CS98000 Registers (Continued)
30
CS98000
B50 B54 B58 B5c B60 B64 B68 B6C B70 B74 B78 B7C C00 C04 C08 C0C C10 C14 C18 C1C C20 C24 C28 C2C C30 C34 C38 C3C C40 C44 C50 C54 C58 D00 D04 D08 D0C D10 D14 D18 D1C WO WO WO WO WO WO WO WO WO WO WO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display Anti-Flicker Anti-Flicker Anti-Flicker Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Vid_Sync Adjust Subpicture_Color0 Subpicture_Color1 Subpicture_Color2 Subpicture_Color3 Subpicture_Color4 Subpicture_Color5 Subpicture_Color6 Subpicture_Color7 Subpicture_Color8 Subpicture_Color9 Subpicture_Color10 Subpicture_Color11 Subpicture_Color12 Subpicture_Color13 Subpicture_Color14 Subpicture_Color15 Subpicture_DCI_Address Subpicture_HLI_Address Subpicture_Control Subpicture_Display_Offset Subpicture_Display_Scale OSD_Status OSD_Control OSD_Color_Number OSD_Color_Data OSD_Region1_Control OSD_Region1_Hlimits OSD_Region1_Vlimits OSD_Region1_DramBase
Table 14. CS98000 Registers (Continued)
31
CS98000
D20 D24 D28 D2C D30 D34 D38 D3C D40 D44 D48 E00 E04 E08 E0C E10 E14 E18 E20 E24 E28 E2C E30 E34 E38 E3C E40 E44 E48 E4C E50 2XXXX 3XXXX R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO RW RW RW RO RW RW R/W R/W On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM RISC0 RISC1 OSD_Region2_Control OSD_Region2_Hlimits OSD_Region2_Vlimits OSD_Region2_DramBase OSD_Region3_Control OSD_Region3_Hlimits OSD_Region3_Vlimits OSD_Region3_DramBase OSD_Blend OSD_Debug1 OSD_Debug2 PCM_Run_Clear PCM_Output_Control PCM_Out_FIFO_Start_Address PCM_Out_FIFO_End_Address PCM_Out_FIFO_Interrupt_Address PCM_Out_FIFO_Current_Address SPDIF_Channel_Status PCM_Input_Control PCM_In_FIFO_Start_Address PCM_In_FIFO_End_Address PCM_In_FIFO_Interrupt_Address PCM_Out_FIFO_Interrupt_Address2 PCM_Out_FIFO_Interrupt_Address3 PCM_In_FIFO_Current_Address SPDIF_Output_Control SPDIF_Output_FIFO_Start_Address SPDIF_Output _FIFO_End_Address SPDIF_Output _FIFO_Current_Address SPDIF_Output _FIFO_Interrupt_Address SPDIF_Output_Add_Block RISC 0 Processor registers RISC 1 Processor registers
Table 14. CS98000 Registers (Continued)
32
CS98000
6. PIN DESCRIPTION
H_D_[15:0] H_CS_[3:0] H_A_[4:0] H_ALE H_RD H_WR H_CKO H_RDY VIN_ D[7:0] VIN_HSNC VIN_VSNC VIN_CLK VIN_FLD CDC_DI CDC_DO CDC_RST CDC_CK CDC_SY M_A_[11:0] M_BS_N M_D_[31:0] M_DQM_[3:0] M_RAS_N M_CAS_N M_WE_N M_AP M_CKE M_CKO NVR_OE_N NVR_WR_N
Host/Loader (30)
Memory IF (57)
Video In (12)
CS98000
HSYNC VSYNC CLK27_O VDAT_[7:0] AUD_BCK AUD_LRCK AUD_DO_[3:0] SPDIF_O AIN_BCK AIN_LRCK AIN_DATA
Video out (11)
CODEC IF (5)
DAC Out (7)
MISC. (41)
XTLCLOCK RST_N IR_IN MFG_TST GPIO D[20-0] _ GPIO H[16-14] _ GPIO_V10 GPIO_[15-10, 8-7, 4-2, 0]
ADC In (3)
Figure 15. CS98000 Pinouts
Table 15 lists the conventions used to identify the pin type and direction.
Pin Type I IS ID IU O O4 O8 T4 B B4 B4U B8U B4S B4SU Pwr Gnd Name_N Input Input, with schmitt trigger Input, with pull down resistor Input, with pull up resistor Output Output - 4 mA drive Output - 8 mA drive Three-Stateable Output - 4mA drive Bi-direction Bi-direction - 4 mA drive Bi-direction - 4 mA drive, with pull-up Bi-direction - 8 mA drive, with pull-up Bi-direction - 4 mA drive, with schmitt trigger Bi-direction - 4 mA drive, with pull-up and Schmitt trigger +2.5 V or +3.3 V power supply voltage Power supply ground Low active Table 15. Pin Type Legend 33 Direction
CS98000
6.1 Pin Assignments Table 16 lists the pin number, pin name, and pin type for the 208 pin CS98000 package. The primary function and pin direction is shown for all signal pins. For some signal pins, a secondary function
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name VDD_PLL M_A_11 M_A_10 GPIO_D18 M_A_9 M_A_8 M_A_7 GPIO_D16 M_A_6 M_A_5 M_A_4 GPIO_D17 M_A_3 M_A_2 M_A_1 M_A_0 GPIO_D19 VSS_IO M_CKO VDD_IO M_BS_N M_CKE M_AP M_RAS_N M_CAS_N GPIO_D20 M_WE_N M_DQM_0 M_DQM_1 GPIO_D0 M_DQM_2 M_DQM_3 M_D_8 GPIO_D1 Type Pwr O8 O8 B4U O8 O8 O8 B4SU O8 O8 O8 B4U O8 O8 O8 O8 B4U Gnd O8 Pwr O8 B8 O8 O8 O8 B4U O8 O8 O8 B4U O8 O8 B8U B4U Primary Function PLL Power 2.5V SDRAM Address[11] SDRAM Address[10] GenioDVD[18] SDRAM Address[9] SDRAM Address[8] SDRAM Address[7] GenioDVD[16] SDRAM Address[6] SDRAM Address[5] SDRAM Address[4] GenioDVD[17] SDRAM Address[3] SDRAM Address[2] SDRAM Address[1] SDRAM Address[0] GenioDVD[19] I/O Ground SDRAM Clock I/O Power 3.3V SDRAM Bank Select SDRAM Clock Enable SDRAM Auto Pre-charge SDRAM Row Strobe SDRAM Column Strobe GenioDVD[20] SDRAM Write Enable SDRAM DQM[0] SDRAM DQM[1] GenioDVD[0] SDRAM DQM[2] SDRAM DQM[3] SDRAM Data[8] GenioDVD[1]
and direction are also shown. For pins having more than one function, the primary function is chosen when the chip is reset.
Dir I O O B O O O B O O O B O O O O B I O I O O O O O B O O O B O O B B
Secondary Function ROM/NVRAM Address[11] ROM/NVRAM Address[10] System Clock PLL Bypass ROM/NVRAM Address[9] ROM/NVRAM Address8] ROM/NVRAM Address[7] ROM/NVRAM Address[6] ROM/NVRAM Address[5] ROM/NVRAM Address[4] ROM/NVRAM Address[3] ROM/NVRAM Address[2] ROM/NVRAM Address[1] ROM/NVRAM Address[0] Memory Clock PLL Bypass
Dir O O I O O O O O O O O O O I
Note
GenioMis(7)
B
ROM/NVRAM Data[8]
B
Table 16. 208-Pin Package Assignments
34
CS98000
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Name VSS_IO VSS_CORE M_D_7 VDD_IO GPIO_D2 M_D_9 VDD_CORE M_D_6 GPIO_D3 M_D_10 M_D_5 M_D_11 GPIO_D4 M_D_4 M_D_12 GPIO_D5 M_D_3 UNUSED UNUSED M_D_13 M_D_2 M_D_14 GPIO_D6 VSS_IO M_D_1 M_D_15 GPIO_D7 M_D_0 VSS_CORE M_D_24 GPIO_D11 VDD_CORE M_D_23 M_D_25 GPIO_D10 M_D_22 M_D_26 M_D_21 GPIO_D9 M_D_27 B8U B8U B8U B4U Gnd B8U B8U B4U B8U Gnd B8U B4U Pwr B8U B8U B4U B8U B8U B8U B4U B8U Type Gnd Gnd B8U Pwr B4U B8U Pwr B8U B4U B8U B8U B8U B4U B8U B8U B4U B8U Primary Function I/O Ground Core Ground SDRAM Data[7] I/O Power 3.3V GenioDVD[2] SDRAM Data[9] Core Power 2.5V SDRAM Data[6] GenioDVD[3] SDRAM Data[10] SDRAM Data[5] SDRAM Data[11] GenioDVD[4] SDRAM Data[4] SDRAM Data[12] GenioDVD[5] SDRAM Data[3] may leave unconnected may leave unconnected SDRAM Data[13] SDRAM Data[2] SDRAM Data[14] GenioDVD[6] I/O Ground SDRAM Data[1] SDRAM Data[15] GenioDVD[7] SDRAM Data[0] Core Ground SDRAM Data[24] GenioDVD[11] Core Power 2.5V SDRAM Data[23] SDRAM Data[23] GenioDVD[10] SDRAM Data[22] SDRAM Data[26] SDRAM Data[21] GenioDVD[9] SDRAM Data[27] B B B B I B B I B I B B I B B B B B B B B ROM/NVRAM Address[23] O ROM/NVRAM Address[18] ROM/NVRAM Address[22] ROM/NVRAM Address[17] O O O ROM/NVRAM Address[19] ROM/NVRAM Address[21] O O ROM/NVRAM Address[20] O ROM/NVRAM Data[0] ROM/NVRAM Data[1] ROM/NVRAM Data[15] B B B B ROM/NVRAM Data[13] ROM/NVRAM Data[2] ROM/NVRAM Data[14] B B B Dir I I B I B B I B B B B B B B B B B ROM/NVRAM Data[3] B ROM/NVRAM Data[4] ROM/NVRAM Data[12] B B ROM/NVRAM Data[10] ROM/NVRAM Data[5] ROM/NVRAM Data[11] B B B ROM/NVRAM Data[6] B ROM/NVRAM Data[9] B ROM/NVRAM Data[7] B Secondary Function Dir Note
Table 16. 208-Pin Package Assignments (Continued)
35
CS98000
Pin 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 Name M_D_20 M_D_28 GPIO_D8 M_D_19 M_D_29 M_D_18 NV_WE_N VSS_CORE M_D_30 VDD_CORE H_ALE M_D_17 M_D_31 M_D_16 GPIO_H14 NV_OE_N VDD_IO H_RD H_WR GPIO_H15 H_RDY VSS_IO H_A_2 GPIO_H16 H_A_1 H_A_0 H_CS_1 H_A_4 VSS_CORE VSS_PLL VDD_PLL H_CS_0 H_A_3 VDD_CORE H_D_15 H_D_14 H_CS_3 H_D_13 H_D_12 Type B8U B8U B4U B8U B8U B8U B4U Gnd B8U Pwr B4U B8U B8U B8U B4U O4 Pwr B4S B4 B4U B4 Gnd B4 B4U B4 B4 B4 B4 Gnd Gnd Pwr B4 B4 Pwr B4 B4 B4 B4S B4 Primary Function SDRAM Data[20] SDRAM Data[28] GenioDVD[8] SDRAM Data[19] SDRAM Data[29] SDRAM Data[18] NVRAM Write Enable Core Ground SDRAM Data[30] Core Power 2.5V Host Address Latch SDRAM Data[18] SDRAM Data[31] SDRAM Data[16] GenioHst[14] ROM/NVRAM Output Enable I/O Power 3.3V Host Read Strobe Host Write Strobe GenioHst[15] Host Ready I/O Ground Host Address[2] GenioHst[16] Host Address[1] Host Address[0] Host Chip Select [1] Host Address[4] Core Ground PLL Ground PLL Power 2.5V Host Chip Select[0] Host Address[3] Core Power 2.5V Host Data[15] Host Data[14] Host Chip Select[3] Host Data[13] Host Data[12] Dir B B B B B B O I B I O B B B B O I O O B I I O B O O O O I I I O O I B B O B B CD Data CD Left Right Clock GenioHst[18] CD Clock CD Error I I B I I 1, 2 1, 2 1 1, 2 1, 2 DVD Start Sector GenioHst[11] I B 1 1 GenioHst[9] GenioHst[8] DVD Error GenioHst[12] B B I B 1 1 1 1 GenioHst[10] B 1 DVD Data Ready O 1 DVD Data Strobe DVD Data Enable I I 1 1 GenioHst[13] ROM/NVRAM Address[13] ROM/NVRAM Decode High ROM/NVRAM Address[12] B O O O ROM/NVRAM Decode Low O ROM/NVRAM Address[14] GenioMis[8] O B ROM/NVRAM Address[15] O Secondary Function ROM/NVRAM Address[16] Dir O Note
Table 16. 208-Pin Package Assignments (Continued)
36
CS98000
Pin 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Name H_D_11 H_CS_2 H_D_10 H_D_9 H_D_8 VSS_IO H_CKO H_D_7 H_D_6 H_D_5 AUD_BCK H_D_4 VSS_CORE H_D_3 AUD_LRCK VDD_CORE H_D_2 VDD_IO H_D_1 AUD_DO_2 H_D_0 AUD_DO_0 AUD_DO_1 AIN_BCK VSS_CORE AIN_LRCK AIN_DATA VDD_CORE CDC_DI VSS_IO CDC_DO VIN_CLK CDC_RST CDC_CK CDC_SY GPIO_V10 GPIO_D15 GPIO_D14 GPIO_D13 VIN_VSNC Type B4 B4 B4 B4 B4 Gnd B4 B4 B4 B4 B4 B4 Gnd B4 O4 Pwr B4 Pwr B4 B4 B4 O4 B4 IU Gnd IU B4U Pwr IU Gnd T4 IU T4 IU B4U B4U B4U B4U B4SU B4U Primary Function Host Data[11] Host Chip Select[2] Host Data[10] Host Data[9] Host Data[8] I/O Ground Host Clock Host Data[7] Host Data[6] Host Data[5] Audio Out Bit Clock Host Data[4] Core Ground Host Data[3] Audio Out LR Clock Core Power 2.5V Host Data[2] I/O Power 3.3V Host Data[1] Audio Out Data[2] Host Data[0] Audio Out Data[0] Audio Out Data[1] Audio In Bit Clock Core Ground Audio In LR Clock Audio In Data Core Power 2.5V Serial CODEC Data In I/O Ground Serial CODEC Data Out Video Input Clock Serial CODEC Reset Serial CODEC Bit Clock Serial CODEC Sync GenioMis[26] GenioDvd[15] GenioDvd[14] GenioDvd[13] Video Input Vsync Dir B O B B B I O B B B O B I B O I B I B O B O O I I I I I I I O I O I B B B B B I GenioMis[25] B GenioMis[0] B GenioMis[1] B DVD Data[1] GenioMis[2] DVD Data[0] I B I 1 1 DVD Data[2] I 1 DVD Data[3] I 1 GenioHst[19] DVD Data[7] DVD Data[6] DVD Data[5] GenioMis[3] DVD Data[4] B I I I B I 1 1 1 1 1 Secondary Function DVD Control Data In GenioHst[17] DVD Control Data Out DVD Control Ready DVD Control Clock Dir I B O I O Note 1, 2 1 1, 2 1, 2 1, 2
Table 16. 208-Pin Package Assignments (Continued)
37
CS98000
Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 Name CLK27_O GPIO_D12 VDD_PLL VSS_PLL VSS_CORE HSYNC VIN_HSYNC VDD_CORE VSYNC VDAT_0 VIN_D0 VDAT_1 VDAT_2 VDAT_3 VIN_D1 VDAT_4 VDAT_5 UNUSED VDAT_6 VDAT_7 GPIO_0 VIN_D2 VSS_CORE AUD_DO_3 VDD_CORE VIN_D3 VDD_IO GPIO_2 VSS_IO GPIO_3 VIN_D4 GPIO_4 SCL SDA GPIO_7 VIN_D5 GPIO_8 AUD_XCLK GPIO_10 VIN_D6 O4 O4 B4U B4U Gnd B4U Pwr B4U Pwr B4U Gnd B4U B4U B4U B4U B4U B4U B4U B4U B4U B4U B4U Type B4U B4U Pwr Gnd Gnd B4U B4U Pwr B4U O4 B4U O4 O4 O4 B4U O4 O4 Primary Function Video Output Clock GenioDvd[12] PLL Power 2.5V PLL Ground Core Ground Video Output Hsync Video Input Hsync Core Power 2.5V Video Output Vsync Video Output Data[0] Video Input Data[0] Video Output Data[1] Video Output Data[2] Video Output Data[3] Video Input Data[1] Video Output Data[4] Video Output Data[5] may leave unconnected Video Output Data[6] Video Output Data[7] General Purpose IO[0] Video Input Data[2] Core Ground Audio Out Data[3] Core Power 2.5V Video Input Data[3] I/O Power 3.3V General Purpose IO[2] I/O Ground General Purpose IO[3] Video Input Data[4] General Purpose IO[4] I2C Clock I2C Data General Purpose IO[7] Video Input Data[5] General Purpose IO[8] Audio 256x/384x Clock General Purpose IO[10] Video Input Data[6] O O B I I O I I I B I B I B B B B I B B B I GenioMis[22] B General Purpose IO[9] B GenioMis[21] B General Purpose IO[5] General Purpose IO[6] B B GenioMis[20] B GenioMis[19] B General Purpose IO[1] B Audio PLL Input Bypass GenioMis[18] I B Dir O B I I I O I I O O I O O O I O O GenioMis[17] B GenioMis[16] B GenioMis[5] B GenioMis[4] GenioMis[24] B B Secondary Function GenioMis[6] Dir B Note
Table 16. 208-Pin Package Assignments (Continued)
38
CS98000
Pin 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Name GPIO_11 GPIO_12 GPIO_13 GPIO_14 VIN_D7 GPIO_15 VSS_CORE IR_IN XTLCLOCK VDD_CORE SPDIF_O RESET_N MFG_TEST VIN_FLD VSS_PLL Type B4U B4U B4U B4U B4U B4U Gnd IS I Pwr O4 IS I ID Gnd Primary Function General Purpose IO[11] General Purpose IO[12] General Purpose IO[13] General Purpose IO[14] Video Input Data[7] General Purpose IO[15] Core Ground Infrared input 27 MHz Clock In Core Power 2.5V S/PDIF Out Reset In (Tie to ground) Video Input Field PLL Ground Dir B B B B I B I I I I O I I I I GenioMis[23] B Secondary Function Dir Note
Table 16. 208-Pin Package Assignments (Continued) Notes: 1. Pin may be used for micro-less DVD loader interface 2. H_D(15:8) pins may be reassigned as GenIOHst(7:0)
39
CS98000
6.2 Miscellaneous Interface Pins These pins are used for used for basic functions such as clock and reset input. See Table 17. The I2C pins are used for both master and slave mode (8-bit slave address is 0x30 for write, and 0x31 for read). 6.3 SDRAM Interface These pins are used to interface the CS98000 with some external SDRAM. The CS98000 can interface with SDRAM of various sizes. Both 16 and 32-bit data width is supported, but best performance is achieved with 32 bits. Follow the instructions in Table 18 on how to interface with any particular configuration of SDRAM.
Pin 186 187 201 202 205 206
Signal Name SCL SDA IR_IN XTLCLOCK RESET_N MFG_TEST
Type B B I I I I I2C Clock I2C Data
Description
Infrared Input, from IR receiver. 27 MHz Clock Input. Reset Input, active low. Manufacturing test pin, should always connect to ground.
Table 17. Miscellaneous Interface Pins
Pin 87, 83, 79, 76, 74, 71, 68, 64, 67, 70, 72, 75, 78, 80, 86, 88, 60, 56, 54, 49, 46, 44, 40, 33, 37, 42, 45, 48, 51, 55, 59. 62 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 16 19 22 21 23 24 25 27 32, 31, 29, 28
Signal Name M_D[31..0]
Type B
Description Memory Data Bus. CS98000 can use all 32 bits or can use only M_D[15..0], in which case M_D[31..16] can be left un-connected.
M_A[11..0]
O
Memory Address Bus. Connect in order starting with M_A[0] to all RAM address pins not already connected to M_BS_L or M_AP. Unused upper M_A pins unconnected. Memory Clock Memory Clock Enable Bank Selection. Always connect to RAM BS or BS0 pin. Memory Auto Pre-charge. Always connect to RAM AP pin. Memory Row Address Strobe Memory Column Address Strobe Memory Write Enable IO Mask of Data Bus M_DQM[3] -> M_D[31:24]
M_CKO M_CKE M_BS_N M_AP M_RAS_N M_CAS_N M_WE_N M_DQM[3..0]
O O O O O O O O
Table 18. SDRAM Interface
40
CS98000
6.4 ROM/NVRAM Interface This is the interface to the non-volatile memory that contains the firmware. See Table 19. It could be either ROM, NVRAM - FLASH, or EEPROM, or any combination of these types of memory. This interface can also connect to SRAM that would emulate a ROM on a development system. The bus width is 8 or 16 bits. Except for the NVM_WE_N and NVM_OE_N pins, all these pins are shared with the DRAM interface, which operates simultaneously with the ROM/NVRAM interface.
Pin 60, 56, 54, 49, 46, 44, 40, 33, 37, 42, 45, 48, 51, 55, 59. 62 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 16 74, 71, 68, 64, 67, 70, 72, 75, 78, 80, 86, 88 83 87 60 62 Signal Name M_D[15..0] Type B
6.5 Video Output Interface This is the interface to a video encoder chip that will send the CS98000 video signals to a TV. See Figure 20. The output format is either CCIR-601 or CCIR-656. The CS98000 supports both master and slave configuration. For CCIR-656 mode, the CS98000 must be the sync master. In this case, the HSYNC and VSYNC pins can be redefined as GPIOs
Description Memory Data Bus. Use M_D[7:0] for 8-bit interface
M_A[11..0]
O
Memory Address Bus[11..0]
M_D[27..16]
O
Memory Address Bus[23..12] For 16-bit data mode, M_D[26:16] is upper word address. For 8-bit data mode, M_D[27:16] is upper byte address. Address decode low. Copy of address MSB. Address decode high. Compliment of address MSB. NVRAM Write Enable. ROM/NVRAM Output Enable.
M_D[30] M_D[31] NVM_WE_N NVM_OE_N
O O O O
Table 19. ROM/NVRAM Interface
.
Pin 154 159 162 173, 172, 170, 169, 167, 166, 165, 163
Signal Name CLK27_O HSYNC VSYNC VDAT[7..0]
Type O B B O 27 Mhz Clock Output.
Description Horizontal Sync. Output when the CS98000 is the video master, input when the video encoder is master. Vertical Sync. Output when the CS98000 is the video master, input when the video encoder is master. Video Data Output[7..0] in Cb,Y,Cr,Y format.
Table 20. Video Output Interface
41
CS98000
6.6 Video Input Interface The CS98000 supports CCIR-601, CIF, and QCIF video input format thought this interface. See Table 21. 6.7 Audio Output/Input Interface This is the audio PCM interface that connects to an audio CODEC. See Table 22. The sample rate and the size of the samples are programmable for both input and output direction.
Pin 145 153 160 207 198, 193, 189, 184, 179, 175, 168, 164
Signal Name VIN_CLK VIN_VSNC VIN_HSNC VIN_FLD VIN_D [7..0]
Type I I I I I Video Input Clock.
Description Video Input Vertical Sync. Video Input Horizontal Sync. Video Input Field. Video Data Input[7..0] in Cb,Y,Cr,Y format.
Table 21. Video Input Interface Pin 191 124 128 135 136 133 177 204 137 Signal Name AUD_XCLK AUD_BCK AUD_LRCK AUD_DO_0 AUD_DO_1 AUD_DO_2 AUD_DO_3 SPDIF_O AIN_BCK Type B O O O O O O O I Description Audio 256x/384x Clock input or output to Serial DAC. When output, is generated from CS98000 internal PLL. Audio Bit Clock output to serial DAC. Audio Out Left/Right Clock to serial DAC. Audio Serial Data Out[0]. Audio Serial Data Out[1]. Audio Serial Data Out[2]. Audio Serial Data Out[3]. S/PDIF Output Audio Input Bit Clock. The CS98000 can be programmed to use the Audio Output function's internally generated bit clock, in which case this pin is not required. Audio Input Left/Right Clock. The CS98000 can be programmed to use the Audio Output function's internally generated LR clock, in which case this pin is not required. Audio Input Data from Serial ADC.
139
AIN_LRCK
I
140
AIN_DATA
I
Table 22. Audio Input/Output Interface
42
CS98000
6.8 AC97/CODEC Interface This serial interface could be used either as a second PCM CODEC interface or as an AC97 serial link to an AC97 compliant CODEC. This interface could control a modem, or a second set of audio channels. Table 23 describes the pin to signal assignments for the AC97/CODEC Interface. 6.9 Host Master/ATAPI Interface This 16-bit parallel host interface allows the CS98000 to be a host master, controlling other devices that would be used on the same system. See Table 24. The interface supports programmable protocols and speeds, including multiplexed and non-multiplexed addressing. Slaves with different protocols can be connected at the same time, controlled by different chip selects.
Pin 142 144 146 147 148
Signal Name CDC_DI CDC_DO CDC_RST CDC_CK CDC_SY
Type I O O I B
Description Serial Data Input from Modem CODEC Serial Data Output to Modem CODEC Reset Output to Modem CODEC Serial Bit Clock input from Modem CODEC Frame Sync, output when CS98000 is master, input when CODEC is master.
Table 23. AC97/CODEC Interface
Pin 111, 115, 101, 106 85 92 93 95 120 102, 107, 97, 99, 100 109, 110, 112, 113, 114, 116, 117, 118, 121, 122, 123, 125, 127, 130, 132, 134
Signal Name H_CS[3..0]
Type O
Description Host Chip Select[3..0]. The host master can be programmed to use a different protocol for each of the 4 chip selects Host address latch enable. Used for modes which multiplex upper address information onto the data lines Host Read Request. Host Write Request. Host Ready. Connect to pull-up or pull-down if host is not used. Host clock out, required for some synchronous slaves Host Address[4..0]. Host Data Bus[15..0]. These pins can also output Host Address during the address phase for multiplexed address/data mode. Tie together to pull-up or pull-down if host is not used.
H_ALE H_RD H_WR H_RDY H_CKO H_A[4..0] H_D[15..0]
O O O I O O B
Table 24. Host Master/ATAPI Interface 43
CS98000
6.10 DVD I/O Channel Interface This interface connects to standard DVD loaders, and consists of three parts: Control, DVD Data and CD Data. (See Table 25.) This interface shares CS98000 pins with the Host Master/ATAPI interface. (See Table 24 on page 43.) The definition of the pins is set via register programming, and the two modes are mutually exclusive. General Purpose Input/Output (GPIO) The CS98000 provides 37 GPIO pins, each with individual output three-state controls. Three-state means that the output driver is turned off or placed in the high-impedance state. Table 26 describes the General Purpose I/O Interface. Additional pins may also be re-defined as GPIO's. 6.11
Pin 121, 122, 123, 125, 127, 130, 132, 134 118 117 116 114 113 112 110 109 106 101 95 93 92
Signal Name H_D[7:0]
Type I
Description DVD_Data[7:0] - DVD data port parallel data input from loader Control port clock to loader Control port ready signal from loader Control port serial command to loader Control port serial status from loader CD error signal from loader CD clock from loader CD left/right clock from loader CD serial data from loader DVD data start sector signal from loader DVD data error signal from loader DVD data ready signal to loader DVD data enable signal from loader DVD data clock from loader
H_D[8] H_D[9] H_D[10] H_D[11] H_D[12] H_D[13] H_D[14] H_D[15] H_CS_0 H_CS_1 H_RDY H_WR H_RD
O I O I I I I I I I O I I
Table 25. DVD I/O Channel Interface Pin 26, 17, 4, 12, 8, 150, 151, 152, 155, 65, 69, 73, 77, 61, 57, 50, 47, 43, 39, 34, 30 98, 94, 89 149 199, 197, 196, 195, 194, 192 190, 188 195, 183, 181 174 Signal Name GPIO_D[20:0] Type B Description 21 General purpose I/O's
GPIO_H[16:14] GPIO_V10 GPIO_[15:10] GPIO_[8:7] GPIO_[4:2] GPIO_0
B B B B B B
3 General purpose I/O's General purpose I/O 6 General purpose I/O's 2 General purpose I/O's 3 General purpose I/O's General purpose I/O
Table 26. General Purpose I/O Interface 44
CS98000
6.12 Power and Ground The CS98000 requires 3 different types of power supplies - PLLs, internal logic and IO pins -. The PLLs and internal logic use 2.5 V power supply, The IO pins use 3.3 V power supply, and are 5 V input tolerant. (See Table 27.)
Pin 1, 105, 158 41, 66, 84, 108, 129, 141, 161, 178, 203 20, 38, 91, 131, 180 104, 157, 208 36, 63, 82, 103, 126, 138, 158, 176, 200 18, 35, 58, 96, 119, 143, 182
Signal Name VDD_PLL VDD_CORE
Type I I 2.5 V for internal PLLs
Description 2.5 V for internal core logic
VDD_IO VSS_PLL VSS_CORE
I I I
3.3 V for I/O's Ground for internal PLLs Ground for internal core logic
VSS_IO
I
Ground for I/Os
Table 27. Power and Ground
45
CS98000
7. PACKAGE SPECIFICATIONS
30.6 0.2 28.00 0.05 3.80(MAX) 3.35 0.05 0.35 0.1
208 1 157 156
28.00 0 .0 5
52 53 104
105
30.6 0 . 2
0.500.05
0.220.05
Detail A
0.15 TYP.
15 0(MIN) R0.15 0.2 (MIN)
10
0.15 TY P.
R0.20
WITH PLATING 0.20 BASE METAL
0.500.1 1.30.1 5
DETAIL A
Figure 16. 208-Pin Package Drawing
46

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